To perform an internal operation, a semiconductor memory device receives an external voltage such as a supply voltage VDD and a ground voltage VSS from outside, and generates an internal voltage to be used for the internal operation. The internal voltage of the memory device may include a core voltage VCORE supplied to a memory core region, a high voltage VPP used for driving a word line, and a back bias voltage VBB supplied as a bulk voltage of an NMOS transistor of the core region.
The core voltage VCORE may be generated by lowering the supply voltage VDD to a predetermined level. However, the high voltage VPP has a higher level than the supply voltage VDD inputted from outside, and the back bias voltage VBB has a lower level than the ground voltage VSS inputted from outside. Therefore, a charge pump circuit is required to supply charges for generating the high voltage VPP and the back bias voltage VBB.
An internal voltage used in a semiconductor memory device may include a negative word line voltage VNWL. The negative word line voltage VNWL is a voltage which is supplied to a word line in a state such as a precharge state in which the word line is not selected, and maintains a lower level than the ground voltage VSS to thereby reduce a leakage current without increasing the threshold voltage of a memory cell transistor.
However, because the negative word line voltage VNWL is generated using the charge pump, as the absolute value of the negative word line voltage VNWL increases, power consumption increases. Further, if a bridge occurs between a word line and a bit line in a state in which the negative word line voltage VNWL is applied to the word line, a potential difference across the bridge increases in proportion to the absolute value of the negative word lines voltage VNWL. Therefore, as the absolute value of the negative word line voltage VNWL increases, a leakage current due to the bridge increases.